Generate

Generate All From Source

Generate a virtual hierarchy for the schematic instances that have no layout counterparts generated and create soft blocks for schematic symbols with no schematic or virtual hierarchy.

Generate Layout Form

Generate Selected From Source

Generate a virtual hierarchy for the selected schematic instances and create soft blocks for schematic symbols with no schematic or virtual hierarchy.

Generate Selected Components Form

Reinitialize

Make collections of design objects based on their cell type and place them around the design boundary.

Reinitialize Floorplan

Load Physical View

Import cellview information from an existing layout cellview.

Load Physical View

Auto Generate Hierarchy

Generate a physical hierarchy by applying common parameters for boundary and pins. In addition, specify the area estimator function to use for all the blocks.

Auto-Generate Hierarchy

Generate Physical Hierarchy

Generate the components in a design while maintaining the hierarchy levels defined in CPH Soft Block mode.

Generate Physical Hierarchy

Manage Hierarchy

Create Virtual Group

Create a group around the selected top-level instances or instances inside a virtual hierarchy. The created group can be opaque or transparent and can be automatically placed when resized.

Create Virtual Group Form

Make Cell

Create new cellviews using virtual hierarchies selected from the top cellview.

Make Cell Form

Make Virtual Hierarchy

Integrate layout hierarchies that were realized outside the design.

Make Virtual Hierarchy Form

Remaster

Replace the selected virtual hierarchy block with the selected layout master that exists on disk.

Remaster Form

I/O Planning

I/O Row Create

Create IO rows for the PAD type siteDefs available in the technology file.

Create IO Row

I/O Pad Placer

Place instances of cell type PAD in IO rows.

IO Pad Placement

Corner Pad Placer

Insert corner cells between IO rows to maintain signal continuity between IO rings.

Corner Pad Placement

Insert I/O Filler

Insert filler cells in the empty spaces between pad instances to maintain signal continuity in the IO row.

Insert Filler Cells

Block Planning

Adjust Boundary

Resize or create the area boundary for the selected virtual hierarchy, the PR boundary for the selected soft block, or the top-level PR boundary.

Adjust Boundary Form

Place Blocks

Automatically place all hard and soft blocks in a design and minimize the wire length and chip area.

Block Placer Form

Load Solutions

Load other solutions that block placer generates.

Load Solutions Form

Report Placement Statistics

Display the placement statistics report after block placement.

None

Adjust Blocks

Adjust the existing floorplan by abutting and pushing the soft blocks in the design.

None

See Adjust Blocks/Pin

Remove Block Overlaps

Remove overlaps and place overlapping hard blocks and soft blocks adjacent to each other.

None

See Remove Block Overlap

Snap Soft Blocks to Grid

Snap soft blocks to the placement grid or to the manufacturing grid.

None

See Snap Soft Blocks to Grid

Pull Soft Blocks inside PR Boundary

Pull the soft blocks overlapping the PR boundary into the core area.

None

See Pull Soft Blocks Inside PR Boundary

Edit Soft Blocks

Modify soft block attributes.

Edit Soft Blocks

Push Into Blocks

Push the top-level implementation of power structures and signal routes into the block level, either as route or as a blockage.

Push into Blocks

Pin Planning

Pin Tool

Create, resize, plan, and optimize pins, edit pin attributes, and set pin location constraints.

None

See Using the Pin Tool

Pin Planner

Assign or refine pin constraints and pin attributes.

Pin Placement Form

Pin Optimization

Position block pins to minimize the net length honoring process rules and design constraints such as min-spacing, min-width, wireType, order, and edge at a particular level in the design.

Pin Placement Form

Pin Checker

Run checks on pins and report the results.

Pin Checker Form

Create/Edit Pin Group Guide

Create or edit pin groups and guides interactively.

Pin Group Guide Form

Compare Pin Group Guides

Compare the pin group guides in two cellviews.

Compare Pin Group Guides

Place Pin Group Guides as Schematic or Symbol

Generate pin group guides and place pins based on their relative positions in the schematic or symbol view.

Pin Group Guide – Place As Schematic/Symbol Form

Create Soft Pins

Create additional soft pins on soft blocks.

Add Soft Pin

Snap Pins

Snap top-level and level-1 pins to the grid appropriate to the block type.

Snap Pins

Label Update

Update pin labels and text displays for clearer visualization.

Label Update Form

Placement Planning

Placement Planning

Define placement locations for transistors and other design elements.

Placement Planning

Auto Place

Access the automatic placement tools to perform standard cell placement or to refine the existing analog device placement.

Automatic Placement

Route Planning

Congestion Analysis

Analyze the routing capacity of a design.

Congestion Analysis

Track Pattern

Select a width spacing pattern for a region or global area that is displayed as tracks on the canvas.

Track Pattern Assistant

Global Route All Nets

Run global route for all the nets in the layout.

Global Route

View

Analyze Connectivity

Draw flight lines between each connected pair of virtual hierarchy groups, soft blocks, or hard blocks.

Select pairs of virtual hierarchy, soft block, or hard block to see the connections between them.

Analyze Connectivity

Block Annotations

Display information about blocks.

Block Annotations Options

Options

Control the display of virtual hierarchies and blocks in a design.

Design Planning and Analysis Options Form