Virtuoso
®
UltraSim Simulator User Guide
Product Version 18.1 January 2019
Index
Symbols
\ forward slash
, comma
; semicolon
: colon
. period
... ellipsis
.acheck
.actnode
.age
.agemethod
.ageproc
.alias
.alter
.bi
.chk_ignore
.chkwindow
.connect
.data
.dcheck
.deltad
.end
.endl
.ends
.eom
.evcd
.global
.hci_only
.hdl
.hier
.hotspot
.ic
.idelay
.in
.inactnode
.include
.lib
.lprobe/.lprint
.macro
.malias
.measure
.measure/power
.minage
.nbti_only
.nodeset
.odelay
.op
.option
ingold
measdgt
numdgt
.options
.options wl
.out
.outz
.para_rpt
.param
.part_rpt
.pbti_only
.pcheck
.print
.probe
.scope
.subckt
.tdelay
.temp
.tfall
.tran
.trise
.triz
.usim_emir
.usim_ir
.usim_nact
.usim_opt (also see options, simulator)
.usim_opt, help
.usim_pa
.usim_pn
.usim_report
.usim_restart
.usim_save
.usim_ta edge
.usim_ta hold
.usim_ta pulsew
.usim_ta setup
.usim_trim
.usim_ups
.usim_vr
.vcd
.vih
.vil
.voh
.vol
` apostrophe
' ' single quotation marks
" " double quotation marks
" quotation mark
( ) parentheses
[ ] brackets, square
{ } braces
* asterisk
* wildcard
*relxpert:
*relxpert: +
/ back slash
& ampersand
# number sign
^ caret
+ plus sign
+config, command line format
+lorder, command line format
+lqtimeout, command line format
+lreport, command line format
+lsuspend, command line format
< > brackets, angle
= equal sign
=log, command line format
| bar
~ tilde
$ dollar sign
$comment
$date
$end
$enddefinitions
$scope
$timescale
$upscope
$var
$version
A
A (Analog)
abstoli
abstolv
AC lifetime and aging model
accuracy
analog
mos_method
settings, UltraSim options
sim_mode
wf_reltol
acheck
active node checking analysis
actnode file
ade
ADE (Analog Design Environment)
advanced analysis, UltraSim
advantages of AgeMOS model
age
aged, model
agemethod
AgeMOS
ageproc
ahdl_include
-ahdllint, command line format
alias
alter
analog
autodetection
design environment
analysis
active node checking
advanced
capacitive current
commands
design checking
dynamic power
info
node activity
parasitic effects on power net wiring
partition and node connectivity
power
power checking
timing
UltraSim, advanced
wasted current
ATFT (Alpha Thin Film Transistor)
autodetection, analog
average, RMS, min, max, peak-to-peak, and integral (see .measure)
avoh
avol
B
B3SOIPD
backannotation, RC
behavioral models, Verilog-A
bi
bipolar junction transistor
argument descriptions
Gummel Poon
HICUM
Mextram
parasitic
quasi-saturation
VBIC99
bisection timing optimization
BJT (Bipolar Junction Transistor)
BJT voltage check
BSIM
1
2
3
3SOI
3V3
4
SPICE
built-in functions, Spectre and SPICE models
bus
node mapping, Verilog netlist
signal notation
buschar
C
C (Celsius)
canalog
canalogr
capacitive current analysis
capacitor
statistical check
voltage check
CCCS (Current-Controlled Current Source)
CCVS (Current-Controlled Voltage Source)
CDS_AUTO_64BIT
cgnd
cgndr
changing resistor, capacitor, or MOSFET device values
check
active node
BJT device voltage
capacitor
statistical
voltage
DC path leakage current
diode voltage
floating gate induced leakage
high impedance node
hold
hot spot node current
JFET voltage
MESFET voltage
MOS device voltage
netlist parameter
over current (excessive current)
over voltage (excessive node voltage)
pulse width
resistor
statistical
voltage
setup
static
Diode voltage
high impedance
maximum leakage path
MOS voltage
NMOS bulk forward-bias
PMOS bulk forward-bias
substrate forward bias
timing edge
checkSysConf
chk_capacitor
file
chk_ignore
chk_resistor
file
chk_window
chkwindow
circuit elements
E
F
G
H
T
W
close
-cmd cmdfile, command line format
CMI (Compiled-Model Interface)
-cmiconfig, command line format
cmin_allnodes
CMOS (Complementary Metal Oxide Semiconductor)
command
descriptions, digital vector format
avoh
avol
chk_ignore
chk_window
enable
hier
hlz
idelay
io
odelay
outz
period
radix
slope
tdelay
tfall
trise
triz
tunit
vih
vil
vname
voh
vol
vref
vth
line format, UltraSim
+config
+lorder
+lqtimeout
+lreport
+lsuspend
=log
-ahdllint
-cmd cmdfile
-cmiconfig
-f
-format fmt
-h
-i
-I dir
-info
-libpath path
-log
-outdir
-outname
-r file
-raw rawDir
-rout
-rtsf
-spectre
-top subckt
-uwifmt name
-v
-vlog Verilog_file
-w
commands
analysis
log file
UltraSim
comment
comment line
command descriptions
signal information file
comparison result waveforms
digital vector file
value change dump file
configuration file, UltraSim
conn
connect
continuous line
command descriptions
signal information file
value change dump file
control
options, .print
conventions
current analysis
capacitive
wasted
current and power, .measure
current-controlled
current source
voltage source
D
DA (Digital Accurate)
data
database options, simulator
buschar
date
DC
a mode
independent sources
lifetime and aging model
path leakage current check
progress report
simulation control options
unstable nodes report
dc
options, simulator
dc
dc_exit
dc_prolong
dc_turbo
homotopy
transient source functions
dc_exit
dc_rpt_num
dc_turbo
dcheck
dcheck file
dcut
debugging, interactive simulation
default values, simulator options
deg_mod
deltad
describe
design, checking analysis
detect
conducting
NMOSFETs
PMOSFETs
device
binning
flash core cell
model options, simulator
deg_mod
diode_method
mos_cap
mos_method
mosd_method
vdd
device_master_name
devices, HSPICE
DF (Digital Fast)
D-FF (Delay-Type Flip Flop)
digital
accurate
extended
fast
vector file
conversion to analog waveform
example
frequently asked questions
general definition
signal
characteristics
states
tabular data
vector patterns
waveforms
Diode
static voltage check
diode
supported models
Level 1
Level 2
Level 3
Level 4
voltage check
diode_method
DRAM (Dynamic Random Access Memory)
DSM (Deep-Submicron)
dsn
file
DSPF (Detailed Standard Parasitic Format)
dump_step
duplicate_subckt
duplicateinstance
duplicateports
DUT (Device Under Test)
DX (Digital Extended)
dynamic power analysis
E
E-element
EKV (Enz-Krummenacher-Vittoz)
elem_compact
elem_i
elemcut_file
elemcut, output file
element, compaction
elements, circuit
bipolar junction transistor
capacitor
current-controlled current source
current-controlled voltage source
diode
independent sources
lossless transmission line
MOSFET
resistor
self inductor
voltage-controlled
capacitor
current source
resistor
voltage source
elements, HSPICE
enable
end
end_bus_symbol
enddefinitions
endl
ends
environment options, simulator
ade
eom
equations
AC lifetime and aging model
age
degradation
quasi-static argument
AgeMOS
DC lifetime and aging model
degradation
proportionality constant
error messages
EVCD
command descriptions
data
port direction and value mapping
signal strength levels
value change data syntax
EVCD (Extended Value Change Dump)
example(s)
.measure
active node checking analysis
advanced analysis
AgeMOS
analog
canalogr
capacitive current analysis
circuit elements
conventions
dc
design checking analysis
BJT voltage check
capacitor voltage check
diode voltage check
MOS voltage check
resistor voltage check
digital vector file commands
diode modeling options
dynamic power analysis
.measure
.probe
elem_compact
enhanced value change dump
flash core cell
floating gate induced leakage current check
hier
hierarchical signal name mapping
hold check
info analysis
interactive mode commands
analysis
general
log file
log
lshort
lvshort
m=mval
method
model_lib
MOSFET modeling options
netlist
node activity analysis
parasitic file parsing options
partition and node connectivity analysis
power
analysis
report format
checking analysis
dc path leakage current check
high impedance node check
hot spot node check
over current check
over voltage check
network
pulse width check
RC reduction options
reliability control statements
running 64-bit mode
selective RC backannotation
setup check
signal information file
sim_mode
simulation
output statements
tolerances
simulation and control statements
speed
static power grid calculator
stitching files
strict_bin
structural Verilog, dummy node connectivity
syntax
Spectre
SPICE
tabular data
timing
analysis
edge check
transient source functions
UltraSim
options
output file
value change dump file
data commands
definition commands
vdd
vh
vl
voltage regulator simulation
warning_limit
wasted current analysis
waveform file options
wildcard
excluding resistors and capacitors
power network detection
RC reduction
exec
exi
exit
exitdc
exp
expected output waveforms
digital vector file
value change dump file
F
-f, command line format
features, UltraSim
F-element
FET (Field Effect Transistor)
file(s)
.ic
.part_rpt
actnode
aged model
chk_capacitor
chk_resistor
configuration
dcheck
digital vector
dsn
elemcut
fsdb
icmd
ilog
log
commands
examples
license
simulator options
meas
mt
nact
netlist.vecerr.trn
netlist.vecexp.trn
nodecut
output
pa
para_rpt
parasitic, parsing options
part_rpt
pcheck
pr
print
rpt_chkdiov
rpt_chkmosv
rpt_chknmosb
rpt_chknmosvgs
rpt_chkpar
rpt_chkpmosb
rpt_chkpmosvgs
rpt_chkrcdelay
rpt_chksubs
rpt_erc
rpt_maxleak
signal information
size, waveform
stitching
ta
tr0ascii
tran
trn
ulog
updating waveform
value change dump
processing
vecerr
veclog
waveform resolution
wdf
filtering routine, static power grid calculator
find and when, .measure
flash core cell
device
models
flattening circuit hierarchy option
floating gate induced leakage current check
flush
force
forcev
format
